1. Field of the Invention
The present invention relates to a microprocessor and a method of processing unaligned data in a microprocessor. In particular, the present invention relates to a technique of aligning unaligned data in a memory system.
2. Description of the Related Art
Microprocessors store multibyte data in memories according to a big endian method or a little endian method. FIGS. 11A, 12A, and 13A show the addresses of data stored in memories based on the big endian method, in which FIG. 11A shows a memory storing word (32-bit) data, FIG. 12A shows a memory storing half-word (16-bit) data, and FIG. 13A shows a memory storing byte (8-bit) data. FIGS. 11B, 12B, and 13B show the addresses of data stored in memories based on the little endian method, in which FIG. 11B shows a memory storing word data, FIG. 12B shows a memory storing half-word data, and FIG. 13B shows a memory storing byte data. Each of these memories has a width of 32 bits and addresses 0 to b (hexadecimal number system).
A memory based on the big endian method places a byte 0 at the highest (leftmost) byte position. A memory based on the little endian method places a byte 0 at the lowest (rightmost) byte position.
FIG. 14A shows a set of word data starting from an address 3. This data is stored in, for example, the memory of FIG. 13A based on the big endian method. Namely, an address-3 section of the word data of FIG. 14A is contained in a row of addresses 0 to 3 in the memory of FIG. 14A, and address-4 to -6 sections of the word data ot FIG. 14A are contained in a row of addresses 4 to 7 in the memory of FIG. 13A. The word data shown in FIG. 14A, therefore, is unaligned data in the memory of FIG. 13A. To align this unaligned data, it is necessary to read the address-3 section and the address-4 to 6 sections from the memory of FIG. 14A and store the address-3 section at bits 31 to 24 in a register and the address-4 to -6 sections at bits 23 to 0 in the register. To align such unaligned data, several related arts have been proposed.
One related art is U.S. Pat. No. 4,814,956 Hansen). Hansen discloses a microprocessor employing special instructions to load unaligned data from a memory into a register in the microprocessor, align the value in the register, and store the aligned value in the memory.
FIG. 14B shows an example of a process of aligning unaligned data according to Hansen. To align unaligned data, the related art consecutively executes instructions of “Load Word Left” and “Load Word Right.” The prior art stores a result of the Load Word Left instruction in an intermediate register and merges it with a result of the Load Word Right instruction. This requires a special shift/merge unit. To store unaligned data in a memory, the related art must consecutively execute the instructions “Store Word Left” and “Store Word Right.” These instructions behave differently from other load and store instructions, and therefore, are difficult to implement in a microprocessor. After loading unaligned data from a memory into a register, the related art must execute shifting and merging operations, to cause a critical path in terms of timing.